1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for correcting data stored in memory cells.
2. Description of the Related Art
Conventionally, in flash memories, which is known as electrically programmable and erasable nonvolatile memories, problems can occur in which a charge state, which is one factor representing a physical quantity corresponding to data to be stored into individual memory cells, is varied by stresses. The stresses can occur because of, for example, electric current/voltage during time transition and/or in the events of a data read and the like, whereby threshold distributions of the individual memory cells deviates from a specified range. This leads to potential problems of causing, for example, delays in access time and read errors. To overcome these problems, U.S. Pat. No. 5,835,413 proposes a technique for performing data correction for a memory cell with a threshold distribution that has been deviated by stresses as described above from a specified range so that the cell is set to be within an original specified range.
Referring now to the U.S. Pat. No. 5,835,413, the data correction for a NOR flash memory will be described hereinbelow. As shown in FIG. 7, the flash memory is configured to include, for example, a memory array 21, a reference array 22, a row decoder 24, a column decoder 23, a voltage switch 26, a command interface 27, and a control engine 28. The memory array 21 has memory cells arranged in a matrix. The reference array 22 contains stored reference data input to one end of a sense circuit 25. The row decoder 24 outputs word line selection signals that individually select word lines, and the column decoder 23 outputs bit-line selection signals that individually select bit lines. The voltage switch 26 has a function of switching among voltages for supply to individual circuits corresponding to individual modes such as program, erase, and read modes, and concurrently has a function of switching among intra-device boosted voltages and among externally supplied high voltages for supply to the circuits. The command interface 27 recognizes commands (individually allocated to operations such as program, erase, and read operations), and outputs signals to the individual circuits so that the device commences the individual operations corresponding to the commands. The control engine 28 serves as a microcontroller for executing a specific algorithm for, for example, executing a program or erase operation as and when the algorithm is necessary.
Basic operations of the individual circuits of the conventional memory are similar to those of an ordinary flash memory. The circuits of the conventional memory have features in that a correction signal CORRECT is input to the control engine 28. Upon input of the correction signal, the memory starts a threshold correction routine for memory cells. The signal is input with a command or the like that has been input through an external source. The proposed memory performs verification and program operations by way of internal operations. From this viewpoint, the proposed memory is similar to an ordinary NOR flash memory with only exceptions being that the proposed memory has additional functions of applying the correction signal CORRECT and the threshold correction routine.
The threshold correction routine will be described hereinbelow with reference to FIGS. 8 and 9. FIG. 9 shows threshold distributions of memory cells, in which the threshold is highest at VT00 and is lowest at VT11. The routine will be described with reference to an example case in which when memory cells required to be within the range of VT01 has caused charge loss and has thereby been shifted to an intermediate state between VT01 and VT10, the threshold is corrected to VT01.
In response to an operation such as input of a command, the routine inputs a correction signal CORRECT to the control engine, and commences a threshold correction operation of the memory cell of interest. First, at step S21, the routine determines whether the state of the memory cell is higher than an upper limit of a distribution range. In more detail, the sense circuit 25 performs a comparison between the memory cell and a reference cell indicative of an upper limit of VT11 to verify whether the state of the memory cell is in an intermediate region between VT11 and VT10. In the present example, the threshold of the memory cell is relatively high, the routine proceeds to step S22 to determine whether the threshold of the memory cell is lower than a lower limit of a distribution range next higher than the first distribution range. In specific, the routine performs a comparison between the state of the memory cell and a reference cell indicative of a lower limit of VT10. In the present example, the threshold of the memory cell is determined higher than the lower limit, so that the routine goes on to step S24 that determines whether the state of the memory cell is in a different state of a multi-valued memory. In more detail, at step S24 the routine determines whether a different distribution range is present. In the present example, since the different distribution range is present, the algorithm proceeds to step S25 that alters the to-be-verified distribution range. (According to the algorithm, while the verification needs to be performed when the memory is a multi-valued memory, the verification need not be performed when the memory is a 2-bit valued memory. As such, when the memory is determined to be a 2-bit valued memory, the routine terminates upon having reached the step S24.) Subsequently, the routine goes again to step S21 that verifies whether the state of the memory cell lies in an intermediate region between VT10 and VT01. That is, the routine performs a comparison between the memory cell and a reference cell indicative of an upper limit of VT10. In the present example, since the threshold of the memory cell is higher than the upper limit, the routine proceeds to step S22 and performs a comparison between the threshold of the memory cell and a reference cell indicative of a lower limit of the VT01. In the present example, since the threshold of the memory cell is lower than the lower limit, the routine goes to step S23 that programs the memory cell until the memory cell reaches a state higher than a lower limit of a next higher distribution range of the current distribution range. That is, at step S23 the memory cell is programmed until the state of the memory cell reaches the lower limit of VT01. Upon completion of the programming, the algorithm terminates. Then, the address is reset and the steps of the routine described above are repeatedly executed, whereby all the memory cells individually undergo the verifications. During the verifications, upon sensing of a memory cell in a state lying outside of the original specified range, the state of the cell is corrected to be within the original range. As above, the routine has been described with reference to the example case where the memory cell is in the intermediate state. However, for a memory cell in a normal state, the routine terminates upon completion of the operation at step S24; that is, programming is not executed.
Thus, according to the conventional technique, the verifications need to be performed for all the individual memory cells to verify data retention states thereof. This gives rise to problems such as that it takes a time for the processing, the shift of threshold due to variations in the charge amount which is one factor representing the physical quantity cannot be sensed in an early stage, and in addition, reduction in power consumption cannot be implemented. In addition, each time a threshold shift is sensed, stresses are imposed on the memory cell, thereby increasing the probability of shifting the threshold of the cell to be out of the specified range. Further, while the conventional technique requires a command or the like to be externally input to commence the algorithm; that is, unless otherwise such a command is input, the algorithm is not executed. This gives rise to a problem of reducing device reliability. Furthermore, in a flash memory, although the conventional technique is capable of performing program operations in units of one bit to a memory cell shifted from a distribution range due to charge loss, erases can only be performed in units of a block (group of memory cells designated to be erased). This gives rise to another problem in that correction cannot be performed in units of a bit for a memory cell shifted from a threshold distribution range by the charge gain.